The present invention relates to the manufacture of chip carrier packages, and in particular forming desired patterns on the packages.
Certain types of conventional semiconductor packages or chip carrier packages (CCPs), such as ball grid array (BGA) packages, include an internal substrate. The substrate includes a core insulative sheet between layers of patterned metal. The patterned metal layer on a top surface of the insulative sheet includes a central rectangular die pad and a plurality of metal traces radiating from the die pad. Each of the traces includes a bond finger adjacent to the die pad. The patterned metal layer on an opposite bottom surface of the insulative sheet includes a plurality of metal traces each terminating at a ball land. The bond fingers and ball lands are typically plated with layers of nickel (Ni) and gold (Au). Metal-lined vias extend vertically through the substrate and electrically connect the metal traces on the top and bottom surfaces of the sheet.
A layer of an epoxy solder mask material is applied over the top and bottom metal layers. The bond fingers, ball lands, and die pad are exposed through openings in the solder mask. A semiconductor die is attached to the metal die pad on the top surface of the sheet. A plurality of bond wires each electrically connect a bond pad of the die to one of the bond fingers of the metal traces on the top surface of the sheet. A hardened molded encapsulant covers the die and bond wires and the entire top surface of the substrate. Solder balls are fused to the ball lands of the metal traces on the bottom surface of the sheet. The solder balls, therefore, are electrically connected to the die through the metal traces, vias, and bond wires.
Metal traces on the top and bottom surface of the substrate are typically formed with a solder mask. FIGS. 1-5 are top plan views of a typical process for removing metal connections. FIG. 1 shows a portion of metal leads or bond fingers 10 on a top surface of a substrate for the CCP. Bond fingers 10, e.g., formed from copper, nickel and gold, are electrically connected by a tie-bar 12, e.g., also formed from copper. A photo-imagable solder mask 14 is positioned over the designed-in shorts 15 and tie-bar 12 such that portions 16 of the designed-in shorts 15 to be subsequently removed remain exposed. Next, in FIG. 2, a photoresist 18 is selectively deposited over designed-in shorts 15 and solder mask 14 such that desired portions of the patterned metal, which include bond fingers 10 to be nickel and gold plated, remain exposed. The photoresist is chosen to be compatible with nickel-gold baths.
In FIG. 3, the exposed portions of copper bond fingers 10 and designed-in shorts 15 are plated with a nickel (Ni)/gold (Au) plating to allow for subsequent wire bonding operations. Because portions 16 are covered by photoresist 18, these portions are not Ni/Au plated. After Ni/Au plating, the photoresist is removed to expose copper portions 16, as shown in FIG. 4. A standard copper etch removal process then etches these portions 16 of designed-in shorts 15, as shown in FIG. 5. Wire bonding, lands, and other types of connections can then be made between a die or chip and the top and/or bottom surfaces of the CCP without subsequent electrical shorting taking place.
This type of conventional process requires the application and removal of photoresist, which increases both costs and time. Photoresist also has limited resolution capabilities, requiring increased tolerance for registration and, as a result of the etch-back process, longer permanent stub remnants remain in the CCP. Accordingly, it is desirable to have a process in which the use of photoresist is not required.
According to an aspect of the present invention, a laser-ablatable solder mask is formed over portions of metal traces, including areas that are to be removed. The solder mask then protects these areas from a subsequent Ni/Au plating, thereby eliminating the need for a photoresist layer. A laser then selectively ablates portions of the solder mask to expose areas of the traces to be removed. A conventional copper etch removal process subsequently etches away these selected areas. In other embodiments, a YAG laser is used, which can remove both portions of the solder mask and the underlying portions of traces.
In one embodiment, metal traces are first patterned on a top and/or bottom surface of a chip carrier package (CCP) substrate. A laser-ablatable solder mask is formed over the traces to expose portions that are to be used for later chip connection. A laser, such as a CO2 or YAG laser, ablates portions of the solder mask to expose designed-in shorts of the traces selected for removal. These exposed areas are removed with a standard etch back process or, if a YAG laser is used, these areas are removed by the YAG laser at the same time the portions of the solder mask are removed.
The present invention eliminates the need for depositing and removing photoresist, which decreases the cost and time to manufacture a CCP as compared with conventional methods. Furthermore, the registrational difference afforded through the use of laser ablation is significantly better than that attainable with photoimaging in conventional processes. This is due to the requirement of an additional photoresist operation. For example, a typical registrational tolerance for photoresist lithography is 75 xcexcm, while a typical registrational tolerance for laser ablation is 25 xcexcm.
In addition, photolithography and etch-back processes typically leave a copper stub (e.g., on the order of 50 xcexcm), resulting from the registrational tolerance differences. These stubs will impact the signal loss/antenna effect. Thus, an additional benefit of the present invention is that the tie bar lengths are reduced, which allows this type of CCP to be used in high speed digital and RF applications.
The present invention will be more fully understood when taken in light of the following detailed description taken together with the accompanying drawings.